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Addendum to the SYM53C810A

Data Manual Version 2.0

December, 1997

This addendum contains new and changed information for the SYM53C810A Data Manual

Version 2.0, published in August 1996. The information will be added to the next version of the

manual. The changes are listed in the order in which their appropriate chapters appear in the data

manual. The Power Management features of the SYM53C810AE enable it to comply with

Microsoft’s PC 97 Hardware Design Guide. This addendum applies to both devices,

SYM53C810A and SYM53C810AE, except where noted.

Chapter 2, Functional Description

Figure 2-4, “Determining the Synchronous Transfer Rate,” was inadvertently omitted. See the

reference to this figure under the main heading “Synchronous Operation.” The

drawing appears

below.

SCF2 SCF1 SCF0 SCF

Divisor

001 1

0 1 0 1.5

011 2

100 3

000 3

TP2 TP1 TP0 XFERP

Divisor

000 4

001 5

010 6

011 7

100 8

101 9

11010

11111

SCLK

SCF

Divider

CCF

Divider

This point

must not

exceed 50

MHz

Synchronous

Divider

Asynchronous

SCSI Logic

Divide by 4

Receive

Clock

Send Clock

(to SCSI bus)

CF2 CCF1 CCF0 SCSI Clock

(MHz)

0 0 0 50.1-66.00

0 0 1 16.67-25.00

0 1 0 25.01-37.50

0 1 1 37.51-50.00

1 0 0 50.01-66.00

Example:

SCLK= 40 MHz, SCF = 1(/1), XFERP = 0(/4),

CCF = 3(37.51-50.00MHz)

Synchronous send rate = (SCLK/SCF)/XFERP =

(40/1)/4=10MB/s

Synchronous receive rate = (SCLK/SCF)/4 =

(40/1)/4=10MB/s

Figure 2-4: Determining the Synchronous Transfer

Rate

1 2 3 4 5 6 7 8

Podsumowanie treści

Strona 1 - December, 1997

1Addendum to the SYM53C810AData Manual Version 2.0December, 1997This addendum contains new and changed information for the SYM53C810A Data ManualVersi

Strona 2 - Power Management

2Achieving Optimal SCSI Send RatesIn this section on page 2-11, the example at the end of the paragraph is incomplete. The TP andSCF bit settings give

Strona 3 - Configuration Registers

3Chapter 3, PCI Functional DescriptionConfiguration RegistersFigure 3-1: PCI Configuration Register Map31 16 15 0Device ID Vendor ID = 1000h 00hStatus

Strona 4 - SYM53C810AE

4Configuration Register ChangesforSYM53C810AERegister 2ChSubsystem Vendor ID (SSVID)Read OnlySVID SVID SVID SVID15-12 11-8 7-4 3-0Default>>>

Strona 5 - Read Only

5Register 08hRevision IDRead Only RID RID RID RID RID RID RID RID76543210Default >>>00100011This field specifies device and revision identif

Strona 6 - Read/Write

6Register 42hPower Management CapabilitiesRead OnlyPMES D2S D1S RES DSI APS PMEC VER15-11 10 9 8-6 5 4 3 2-0Default >>>00000001This register

Strona 7

7Bit 15 PME Status (PST)The device always returns a 0 for this bit, indicating that PME signal generation is not sup-ported from D3cold.Bits 14-13 Da

Strona 8

8Chapter 5, Operating RegistersOn page 5-12, the formula given to calculate the synchronous send and receive rates is incorrect.The correct formula is

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