Avago-technologies LSI53C896 Instrukcja Użytkownika
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- Strona / 366
- Spis treści
- BOOKMARKI
- September 2003 1
- Version 3.3 1
- Preface iii 3
- Revision Record 5
- Contents 7
- Contents ix 9
- Chapter 1 19
- Introduction 19
- 1-2 Introduction 20
- General Description 1-3 21
- 1.2 Benefits of Ultra2 SCSI 22
- 1.4 TolerANT 23
- Technology 23
- 1.5 LSI53C896 Benefits Summary 24
- 1.5.2 PCI Performance 25
- 1.5.3 Integration 26
- 1.5.4 Ease of Use 26
- 1.5.5 Flexibility 27
- 1.5.6 Reliability 28
- 1.5.7 Testability 28
- Chapter 2 29
- Functional Description 29
- 2-2 Functional Description 30
- 2.1.1 PCI Addressing 31
- 2-4 Functional Description 32
- 2-6 Functional Description 34
- 2-8 Functional Description 36
- 2-10 Functional Description 38
- 2.1.3 Internal Arbiter 39
- 2.1.4 PCI Cache Mode 39
- 2-12 Functional Description 40
- 2.1.4.5 Examples 43
- 2.2.1 SCRIPTS Processor 48
- 2.2.2 Internal SCRIPTS RAM 49
- 2-22 Functional Description 50
- 2-24 Functional Description 52
- 2.2.8 Load/Store Instructions 53
- 2.2.10 SCSI Loopback Mode 54
- 2.2.11 Parity Options 55
- Table 2.4 SCSI Parity Control 57
- 2-30 Functional Description 58
- 2.2.12 DMA FIFO 59
- 2.2.13 Data Paths 60
- Counter, which 61
- 2-34 Functional Description 62
- 2.2.14 SCSI Bus Interface 63
- LSI53C8XX 65
- SN75976A2 65
- 2.2.16 Synchronous Operation 68
- 2-42 Functional Description 70
- 2.2.17 Interrupt Handling 71
- 2-44 Functional Description 72
- 2-46 Functional Description 74
- 2-48 Functional Description 76
- 2.2.18 Interrupt Routing 78
- 2.2.19 Chained Block Moves 80
- 2-54 Functional Description 82
- 2.3 Parallel ROM Interface 83
- 2.4 Serial EEPROM Interface 85
- 2.5 Power Management 86
- 2.5.1 Power State D0 87
- 2.5.2 Power State D1 87
- 2.5.3 Power State D2 88
- 2.5.4 Power State D3 88
- Chapter 3 89
- Signal Descriptions 89
- 3-2 Signal Descriptions 90
- 3.2 PCI Bus Interface Signals 93
- 3.2.4 Arbitration Signals 96
- 3.2.5 Error Reporting Signals 97
- 3.2.6 Interrupt Signals 98
- 3.3.1 SCSI Function A Signals 101
- Signals group 103
- 3.3.2 SCSI Function B Signals 104
- 3.5 Test Interface Signals 108
- 3.6 Power and Ground Signals 109
- 3.7 MAD Bus Programming 110
- 3-24 Signal Descriptions 112
- Chapter 4 113
- Registers 113
- Registers:0x00–0x01 114
- Registers:0x02–0x03 115
- Registers:0x04–0x05 115
- 4-4 Registers 116
- Registers:0x06–0x07 117
- Register: 0x08 118
- Registers:0x09–0x0B 119
- Register: 0x0C 119
- Register: 0x0D 120
- Register: 0x0E 120
- Register: 0x0F 121
- Registers:0x10–0x13 121
- Registers:0x14–0x1B 121
- Registers:0x1C–0x23 122
- Registers:0x24–0x27 122
- Registers:0x28–0x2B 122
- Registers:0x2C–0x2D 123
- Registers:0x2E–0x2F 124
- Registers:0x30–0x33 125
- Register: 0x34 126
- Registers:0x35–0x3B 126
- Register: 0x3C 126
- Register: 0x3D 127
- Register: 0x3E 127
- Register: 0x3F 128
- Register: 0x40 128
- Register: 0x41 128
- Registers:0x42–0x43 129
- Registers:0x44–0x45 130
- 4.2 SCSI Registers 131
- Table 4.2 SCSI Register Map 132
- Register: 0x00 133
- 4-22 Registers 134
- SCSI Registers 4-23 135
- Register: 0x01 136
- SCSI Registers 4-25 137
- 4-26 Registers 138
- Register: 0x02 139
- 4-28 Registers 140
- SCSI Registers 4-29 141
- Register: 0x03 142
- Register: 0x04 144
- Register: 0x05 145
- Register: 0x06 149
- Register: 0x07 149
- Register: 0x09 151
- Register: 0x0A 152
- Register: 0x0B 153
- 4-42 Registers 154
- SCSI Registers 4-43 155
- SCSI Registers 4-45 157
- SCSI Registers 4-49 161
- Register: 0x14 162
- SCSI Registers 4-51 163
- 4-52 Registers 164
- Register: 0x15 165
- Register: 0x16 166
- Register: 0x17 167
- Register: 0x18 167
- Register: 0x19 168
- Register: 0x1A 168
- SCSI Registers 4-57 169
- Register: 0x1B 170
- Registers:0x1C–0x1F 171
- Register: 0x20 172
- Register: 0x21 173
- Register: 0x22 175
- Register: 0x23 176
- Registers:0x24–0x26 177
- Register: 0x27 178
- Registers:0x2C–0x2F 179
- Registers:0x34–0x37 180
- Register: 0x38 180
- 4-70 Registers 182
- Register: 0x39 183
- Register: 0x3A 184
- Register: 0x3B 184
- SCSI Registers 4-73 185
- 4-74 Registers 186
- Registers:0x3C–0x3F 187
- SCSI Registers 4-77 189
- Register: 0x42 191
- 4-80 Registers 192
- SCSI Registers 4-81 193
- Register: 0x43 194
- Register: 0x44 195
- Register: 0x45 196
- Register: 0x46 197
- Register: 0x47 197
- 4-86 Registers 198
- Register: 0x48 199
- Register: 0x49 200
- Register: 0x4A 203
- Register: 0x4B 203
- Register: 0x4C 204
- Register: 0x4D 205
- Register: 0x4E 207
- 4-96 Registers 208
- Register: 0x4F 209
- 4-98 Registers 210
- Registers:0x50–0x51 211
- Register: 0x52 212
- Register: 0x53 212
- Registers:0x54–0x55 213
- Register: 0x56 213
- 4-102 Registers 214
- Register: 0x57 215
- 4-104 Registers 216
- Registers:0x58–0x59 217
- Registers:0x5A–0x5B 217
- Registers:0x5C–0x5F 218
- Registers:0x60–0x9F 218
- 4.3 64-Bit SCRIPTS Selectors 219
- Registers:0xA4–0xA7 220
- Registers:0xA8–0xAB 220
- Registers:0xAC–0xAF 221
- Registers:0xB0–0xB3 221
- Registers:0xB4–0xB7 222
- Registers:0xB8–0xBB 222
- Registers:0xBC–0xBF 222
- Registers:0xC0–0xC3 223
- Registers:0xC4–0xC7 223
- Registers:0xC8–0xCB 224
- Registers:0xCC–0xCF 225
- Registers:0xD0–0xD3 226
- Registers:0xD4–0xD7 226
- Registers:0xD8–0xDA 227
- Register: 0xDB 227
- Registers:0xDC–0xDF 228
- Registers:0xE0–0xFF 228
- Chapter 5 229
- SCSI SCRIPTS Instruction Set 229
- 5.1 SCSI SCRIPTS 230
- SCSI SCRIPTS 5-3 231
- 5.2 Block Move Instructions 233
- Block Move Instructions 5-7 235
- Command Not Used 235
- Don’t Care Table Offset 235
- 00 Byte Count 236
- Physical Data Address 236
- OPC Opcode 27 238
- Target Mode 238
- Block Move Instructions 5-11 239
- OPC Instruction Defined 240
- 0 CHMOV/CHMOV64 240
- 1 MOVE/MOVE64 240
- 5.2.2 Second Dword 242
- 5.2.3 Third Dword 242
- 5.3 I/O Instructions 243
- I/O Instructions 5-19 247
- Absolute Alternate Address 248
- I/O Instructions 5-21 249
- Command Table Offset 249
- Absolute Jump Offset 249
- 5.3.2 Second Dword 250
- 5.4 Read/Write Instructions 251
- 5.4.2 Second Dword 252
- 5.5.1 First Dword 255
- from the current 258
- (using addition or 259
- 5.5.2 Second Dword 261
- 5.5.3 Third Dword 261
- 5.6 Memory Move Instructions 262
- 5.6.1 First Dword 263
- 5.6.3 Second Dword 264
- 5.7 Load/Store Instructions 265
- 5.7.1 First Dword 266
- Load/Store Instructions 5-39 267
- 5.7.2 Second Dword 268
- Chapter 6 269
- Specifications 269
- Figure 6.1 LVD Driver 271
- Figure 6.2 LVD Receiver 272
- Table 6.6 Input Capacitance 272
- GPIO4, MAD[7:0] 273
- , MWE/, TDO 273
- TEST_HSC 274
- , TEST_RST/, TMS 274
- 6-10 Specifications 278
- 6.3 AC Characteristics 279
- Figure 6.8 External Clock 280
- Table 6.14 External Clock 280
- Figure 6.9 Reset Input 281
- Table 6.15 Reset Input 281
- • Target Timing 282
- 6.4.1 Target Timing 283
- 6.4.2 Initiator Timing 290
- (Addr drvn by LSI53C896; 301
- 6.4.3 External Memory Timing 306
- 6-40 Specifications 308
- Master-Addr; 309
- (Driven by Master-Addr; 309
- Data Driven by Memory) 309
- 6-42 Specifications 310
- 6-44 Specifications 312
- (Addr driven by LSI53C896; 315
- 6-50 Specifications 318
- (Addr Driven by LSI53C896 319
- 6-52 Specifications 320
- (Addr driven by LSI53C896 323
- (Driven by LSI53C896) 325
- 6.5 SCSI Timing Diagrams 328
- 6.6 Package Drawings 335
- 6-70 Specifications 338
- Package Drawings 6-71 339
- 6-72 Specifications 340
- Appendix A 341
- Register Summary 341
- A-6 Register Summary 346
- Appendix B 347
- External Memory Interface 347
- Diagram Examples 347
- MAD[2:0] 350
- IX-2 Index 352
- Index IX-3 353
- Numerics 354
- Index IX-5 355
- IX-6 Index 356
- Index IX-7 357
- IX-8 Index 358
- Index IX-9 359
- IX-10 Index 360
- Index IX-11 361
- IX-12 Index 362
- Index IX-13 363
- IX-14 Index 364
- Customer Feedback 365
Podsumowanie treści
®DB14-000083-04LSI53C896PCI to Dual ChannelUltra2 SCSIMultifunction ControllerTECHNICALMANUALSeptember 2003Version 3.3
x ContentsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Chapter 6 Specifications6.1 DC Characteristics 6-16.2 TolerAN
3-12 Signal DescriptionsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.3.2.8 SCSI Function B GPIO SignalsTable 3.9 de
SCSI Bus Interface Signals 3-13Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.3.3 SCSI Bus Interface SignalsThe SCSI
3-14 Signal DescriptionsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 3.11 describes the signals for the SCSI
SCSI Bus Interface Signals 3-15Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.A_SCTRL Signals – Table 3.12 describes
3-16 Signal DescriptionsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.3.3.2 SCSI Function B SignalsThis section desc
SCSI Bus Interface Signals 3-17Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.B_DIFFSENS Y21 I N/A SCSI Function B Di
3-18 Signal DescriptionsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 3.14 describes the SCSI Function B_SCRTL
Flash ROM and Memory Interface Signals 3-19Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.3.4 Flash ROM and Memory In
3-20 Signal DescriptionsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.3.5 Test Interface SignalsThis section describ
Power and Ground Signals 3-21Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.3.6 Power and Ground SignalsTable 3.17 de
xiVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figures1.1 Typical LSI53C896 System Application 1-21.2 Typical LSI53
3-22 Signal DescriptionsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.3.7 MAD Bus ProgrammingThe MAD[7:0] pins, in a
MAD Bus Programming 3-23Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.• MAD[3:1] – These pins set the size of the ex
3-24 Signal DescriptionsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller 4-1Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
4-2 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.All PCI-compliant devices, such as the LSI53C896, must su
PCI Configuration Registers 4-3Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Registers:0x02–0x03Device IDRead OnlyDID
4-4 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.R Reserved 5WIE Write and Invalidate Enable 4This bit all
PCI Configuration Registers 4-5Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Registers:0x06–0x07StatusRead/WriteReads
4-6 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.DT[1:0] DEVSEL/ Timing [10:9]These bits encode the timing
PCI Configuration Registers 4-7Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Registers:0x09–0x0BClass CodeRead OnlyCC
xiiVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.6.9 Reset Input 6-136.10 Interrupt Output 6-146.11 PCI Configuration
4-8 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x0DLatency TimerRead/WriteLT Latency Timer [7:
PCI Configuration Registers 4-9Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x0FNot SupportedRegisters:0x1
4-10 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Registers:0x1C–0x23Base Address Register Two (SCRIPTS RA
PCI Configuration Registers 4-11Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Registers:0x2C–0x2DSubsystem Vendor IDR
4-12 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Registers:0x2E–0x2FSubsystem IDRead OnlySID Subsystem ID
PCI Configuration Registers 4-13Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Registers:0x30–0x33Expansion ROM Base A
4-14 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x34Capabilities PointerRead OnlyCP Capabiliti
PCI Configuration Registers 4-15Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x3DInterrupt PinRead OnlyIP
4-16 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x3FMax_LatRead OnlyML Max_Lat [7:0]This regis
PCI Configuration Registers 4-17Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Registers:0x42–0x43Power Management Cap
xiiiVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.6.32 Slow Memory (≥ 128 Kbytes) Write Cycle 6-576.32 Slow Memory (
4-18 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Registers:0x44–0x45Power Management Control/Status (PMCS
SCSI Registers 4-19Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x46Bridge Support Extensions (PMCSR_BSE)
4-20 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 4.2 SCSI Register Map31 16 15 0SCNTL3 SCNTL2 SCNTL
SCSI Registers 4-21Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x00SCSI Control Zero (SCNTL0)Read/WriteA
4-22 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Full Arbitration, Selection/Reselection1.The LSI53C896 S
SCSI Registers 4-23Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.WATN Select with SATN/ on a Start Sequence 4When th
4-24 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.TRG Target Mode 0This bit determines the default operati
SCSI Registers 4-25Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.DHP Disable Halt on Parity Error or ATN (Target Onl
4-26 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.data received for odd parity. This bit is used for diagn
SCSI Registers 4-27Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.handshaking. The determination of whether the trans
xivVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
4-28 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.boundary, the LSI53C896 SCSI function stores the lastbyt
SCSI Registers 4-29Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.VUE1 Vendor Unique Enhancement, Bit 1 1This bit dis
4-30 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x03SCSI Control Three (SCNTL3)Read/WriteUSE U
SCSI Registers 4-31Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.CCF[2:0] Clock Conversion Factor [2:0]These bits se
4-32 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x04SCSI Chip ID (SCID)Read/WriteR Reserved 7R
SCSI Registers 4-33Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x05SCSI Transfer (SXFER)Read/WriteNote:
4-34 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.(This SCSI synchronous core clock is determined inSCNTL3
SCSI Registers 4-35Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.MO[4:0] Max SCSI Synchronous Offset [4:0]These bits
4-36 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 4.5 Maximum Synchronous OffsetMO4 MO3 MO2 MO1 MO0
SCSI Registers 4-37Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x06SCSI Destination ID (SDID)Read/WriteR
xvVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Tables2.1 PCI Bus Commands and Encoding Types 2-52.2 PCI Cache Mode
4-38 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.R Reserved [7:5]GPIO General Purpose I/O [4:0]These bits
SCSI Registers 4-39Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.The SCSI First Byte Received (SFBR) is not writable
4-40 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x0ASCSI Selector ID (SSID)Read OnlyVAL SCSI V
SCSI Registers 4-41Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x0BSCSI Bus Control Lines (SBCL)Read Onl
4-42 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.The DIP bit in the Interrupt Status Zero (ISTAT0) regist
SCSI Registers 4-43Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.R Reserved 1IID Illegal Instruction Detected 0This
4-44 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.• A Memory Move instruction is executed with one ofthe r
SCSI Registers 4-45Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.register, and then to the SCSI bus. The SODR buffer
4-46 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x0ESCSI Status One (SSTAT1)Read OnlyFF[3:0] F
SCSI Registers 4-47Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.SDP0L Latched SCSI Parity 3This bit reflects the SCS
xviVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.6.1 Absolute Maximum Stress Ratings 6-26.2 Operating Conditions 6-2
4-48 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x0FSCSI Status Two (SSTAT2)Read OnlyILF SIDL
SCSI Registers 4-49Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.FF4 FIFO Flags, Bit 4 4This is the most significant
4-50 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Registers:0x10–0x13Data Structure Address (DSA)Read/Writ
SCSI Registers 4-51Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.4.If the SCSI Interrupt Pending bit is set, then re
4-52 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.external processor may also notify the LSI53C896 SCSIfun
SCSI Registers 4-53Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.• A SCSI gross error occurs• An unexpected disconne
4-54 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.SRUN SCRIPTS Running 1This bit indicates whether or not
SCSI Registers 4-55Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x17Mailbox One (MBOX1)Read/WriteMBOX1 Ma
4-56 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x19Chip Test One (CTEST1)Read OnlyFFL Byte Fu
SCSI Registers 4-57Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.CM Configured as Memory 4This bit is defined as the c
xviiVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.6.29 Burst Write, 32-Bit Address and Data 6-346.30 Burst Write, 64
4-58 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.TEOP SCSI True End of Process 2This bit indicates the st
SCSI Registers 4-59Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.CLF Clear DMA FIFO 2When this bit is set, all data
4-60 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.During any Memory-to-Memory Move operation, thecontents
SCSI Registers 4-61Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Step 1.Subtract the seven least significant bits of
4-62 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Move operation. The Data Structure Address (DSA) andTemp
SCSI Registers 4-63Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x22Chip Test Five (CTEST5)Read/WriteADCK
4-64 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.the DMAWR signal indicates that data is transferred from
SCSI Registers 4-65Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Registers:0x24–0x26DMA Byte Counter (DBC)Read/Write
4-66 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x27DMA Command (DCMD)Read/WriteDCMD DMA Comma
SCSI Registers 4-67Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Registers:0x2C–0x2FDMA SCRIPTS Pointer (DSP)Read/Wr
xviiiVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
4-68 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Registers:0x34–0x37Scratch Register A (SCRATCHA)Read/Wri
SCSI Registers 4-69Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.asserted during start-of-transfer and end-of-transf
4-70 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.DIOM Destination I/O-Memory Enable 4This bit is defined a
SCSI Registers 4-71Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.LSI53C896 SCSI function to automatically begin fetc
4-72 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.The INTA/ and INTB/ outputs are latched. When asserted,
SCSI Registers 4-73Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.PFEN Prefetch Enable 5Setting this bit enables an 8
4-74 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.IRQM IRQ Mode 3When set, this bit enables a totem pole d
SCSI Registers 4-75Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.If the COM bit is cleared, do not access this regis
4-76 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x40SCSI Interrupt Enable Zero (SIEN0)Read/Wri
SCSI Registers 4-77Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.SGE SCSI Gross Error 3The following conditions are
LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller 1-1Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
4-78 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x41SCSI Interrupt Enable One (SIEN1)Read/Writ
SCSI Registers 4-79Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.HTH Handshake-to-Handshake Timer Expired 0The hands
4-80 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.CMP Function Complete 6This bit is set when an arbitrati
SCSI Registers 4-81Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.• Residual data in the synchronous data FIFO – atra
4-82 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x43SCSI Interrupt Status One (SIST1)Read Only
SCSI Registers 4-83Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x44SCSI Longitudinal Parity (SLPAR)Read/
4-84 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.The longitudinal parity checks are meant to provide anad
SCSI Registers 4-85Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x46Chip Type (CTYPE)Read OnlyTYP Chip Ty
4-86 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.To set the GPIO registers, follow these steps:1. Read th
SCSI Registers 4-87Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x48SCSI Timer Zero (STIME0)Read/WriteHTH
iiVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.This document contains proprietary information of LSI Logic Corporat
1-2 IntroductionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.to meet the flexibility requirements of SCSI-3 and Ultr
4-88 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.SEL[3:0] Selection Time-Out [3:0]These bits select the S
SCSI Registers 4-89Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.HTH[7:4], SEL[3:0],GEN[3:0]11. These values are cor
4-90 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.HTHSF Handshake-to-Handshake Timer Scale Factor 4Setting
SCSI Registers 4-91Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x4AResponse ID Zero (RESPID0)Read/WriteR
4-92 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x4CSCSI Test Zero (STEST0)Read OnlySSAID SCSI
SCSI Registers 4-93Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.to request data transfers. If the LSI53C896 SCSI is
4-94 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.QEN SCLK Quadrupler Enable 3This bit, when set, powers u
SCSI Registers 4-95Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x4ESCSI Test Two (STEST2)Read/WriteSCE S
4-96 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.AWS Always Wide SCSI 2When this bit is set, all SCSI inf
SCSI Registers 4-97Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x4FSCSI Test Three (STEST3)Read/WriteTE
General Description 1-3Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 1.2 Typical LSI53C896 Board ApplicationN
4-98 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.DSI Disable Single Initiator Response 4If this bit is se
SCSI Registers 4-99Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.SCSI Output Data Latch (SODL) register cause the en
4-100 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Register: 0x52SCSI Test Four (STEST4)Read OnlySMODE[1:0
SCSI Registers 4-101Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Registers:0x54–0x55SCSI Output Data Latch (SODL)Re
4-102 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.This bit also enables the flushing mechanism to flushdata
SCSI Registers 4-103Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.R Reserved [3:2]DILS Disable Internal Load/Store 1
4-104 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.R Reserved [6:4]DDAC Disable Dual Address Cycle (DDAC)
SCSI Registers 4-105Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Registers:0x58–0x59SCSI Bus Data Lines (SBDL)Read
4-106 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Registers:0x5C–0x5FScratch Register B (SCRATCHB)Read/Wr
64-Bit SCRIPTS Selectors 4-107Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.4.3 64-Bit SCRIPTS SelectorsThe followin
1-4 IntroductionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.• Improved PCI Caching design – improves PCI bus effici
4-108 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Writes to the MMRS register are unaffected. Clearing th
64-Bit SCRIPTS Selectors 4-109Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.[16:23] of the SCRIPTS Fetch Selector (S
4-110 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Registers:0xB4–0xB7Dynamic Block Move Selector (DBMS)Re
Phase Mismatch Jump Registers 4-111Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.4.4 Phase Mismatch Jump RegistersEi
4-112 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.inbound (data in, status, message in) phase mismatch(PM
Phase Mismatch Jump Registers 4-113Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Registers:0xCC–0xCFUpdated Address
4-114 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Registers:0xD0–0xD3Entry Storage Address (ESA)Read/Writ
Phase Mismatch Jump Registers 4-115Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Registers:0xD8–0xDASCSI Byte Count
4-116 RegistersVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Registers:0xDC–0xDFCumulative SCSI Byte Count (CSBC)Rea
LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller 5-1Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Benefits of LVDlink Technology 1-5Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.1.3 Benefits of LVDlink TechnologyThe
5-2 SCSI SCRIPTS Instruction SetVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.5.1 SCSI SCRIPTSTo operate in the SCSI
SCSI SCRIPTS 5-3Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.DMA SCRIPTS Pointer Save (DSPS) register. The third wo
5-4 SCSI SCRIPTS Instruction SetVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.interrupts the host CPU and waits for
Block Move Instructions 5-5Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.5.2 Block Move InstructionsFor Block Move i
5-6 SCSI SCRIPTS Instruction SetVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.IndirectWhen set, the 32-bit user data
Block Move Instructions 5-7Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Use the signed integer offset in bits [23:0
5-8 SCSI SCRIPTS Instruction SetVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.64-Bit AddressingIf the enable 64-bit
Block Move Instructions 5-9Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Index Mode 0 (64TIMOD clear) table entry fo
5-10 SCSI SCRIPTS Instruction SetVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.OPC Opcode 27This 1-bit field defines t
Block Move Instructions 5-11Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.The LSI53C896 verifies that it is connected
1-6 IntroductionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.The benefits of TolerANT technology include increased i
5-12 SCSI SCRIPTS Instruction SetVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Initiator ModeThe LSI53C896 verifies t
Block Move Instructions 5-13Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.SCSIP[2:0] SCSI Phase [26:24]This 3-bit fie
5-14 SCSI SCRIPTS Instruction SetVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.5.2.2 Second DwordFigure 5.3 Block Mo
I/O Instructions 5-15Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.5.3 I/O InstructionsThis section contains informa
5-16 SCSI SCRIPTS Instruction SetVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.arbitration, it fetches the next inst
I/O Instructions 5-17Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Clear InstructionWhen the SACK/ or SATN/ bits are
5-18 SCSI SCRIPTS Instruction SetVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.DMA Next Address (DNAD) register. Man
I/O Instructions 5-19Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.SCSI Control Zero (SCNTL0) register is cleared. W
5-20 SCSI SCRIPTS Instruction SetVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.SCSI Transfer (SXFER) register. The c
I/O Instructions 5-21Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table RelativeTreats the alternate jump address a
LSI53C896 Benefits Summary 1-7Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.• Includes 8 Kbytes of internal RAM for S
5-22 SCSI SCRIPTS Instruction SetVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.R Reserved [8:7]A Set/Clear SACK/ 6R
Read/Write Instructions 5-23Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.5.4 Read/Write InstructionsThe Read/Write
5-24 SCSI SCRIPTS Instruction SetVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.ImmD Immediate Data [15:8]This 8-bit
Read/Write Instructions 5-25Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.• Write one byte (value contained within t
5-26 SCSI SCRIPTS Instruction SetVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Miscellaneous Notes:Substitute the de
Transfer Control Instructions 5-27Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.5.5.1 First DwordFigure 5.9 Transfer
5-28 SCSI SCRIPTS Instruction SetVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.When the JUMP64 instruction is used,
Transfer Control Instructions 5-29Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.If the comparisons are false, the LS
5-30 SCSI SCRIPTS Instruction SetVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.RA Relative Addressing Mode 23When th
Transfer Control Instructions 5-31Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.A relative transfer can be to any ad
1-8 IntroductionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.• Performs zero wait-state bus master data bursts up t
5-32 SCSI SCRIPTS Instruction SetVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.CD Compare Data 18When this bit is se
Transfer Control Instructions 5-33Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.DC Data Compare Value [7:0]This 8-bi
5-34 SCSI SCRIPTS Instruction SetVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.5.6 Memory Move InstructionsFor Memor
Memory Move Instructions 5-35Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.5.6.1 First DwordFigure 5.12 Memory Move
5-36 SCSI SCRIPTS Instruction SetVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.source or destination. In this way, r
Load/Store Instructions 5-37Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.5.6.4 Third DwordFigure 5.14 Memory Move I
5-38 SCSI SCRIPTS Instruction SetVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.boundaries. The memory address may no
Load/Store Instructions 5-39Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.When this bit is set, the chip determines
5-40 SCSI SCRIPTS Instruction SetVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.5.7.2 Second DwordFigure 5.16 Load/St
LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller 6-1Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
LSI53C896 Benefits Summary 1-9Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.• Three programmable SCSI timers: Select/
6-2 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 6.1 Absolute Maximum Stress RatingsSymbol Param
DC Characteristics 6-3Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Note: VCM= 0.7–1.8 V (Common Mode, nominal ~1.2
6-4 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.2 LVD ReceiverVCM+−++−−VI2VI2+−Table 6.5 A a
DC Characteristics 6-5Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 6.7 Bidirectional Signals – GPIO0_FETCH/,
6-6 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 6.9 Bidirectional Signals – AD[63:0], C_BE[7:0]
DC Characteristics 6-7Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 6.11 Output Signals – INTA, INTB, ALT_INTA
6-8 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.6.2 TolerANT Technology Electrical CharacteristicsThe
TolerANT Technology Electrical Characteristics 6-9Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.3 Rise and
6-10 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.5 Hysteresis of SCSI ReceiversFigure 6.6 In
AC Characteristics 6-11Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.7 Output Current as a Function of Outp
1-10 IntroductionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.1.5.6 ReliabilityThe following features enhance the r
6-12 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.8 External ClockTable 6.14 External Clock11
AC Characteristics 6-13Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 6.15 and Figure 6.9 provide Reset Input t
6-14 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 6.16 and Figure 6.10 provide Interrupt Output
PCI and External Memory Interface Timing Diagrams 6-15Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.– Operating Regi
6-16 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.11 PCI Configuration Register ReadTable 6.17
PCI and External Memory Interface Timing Diagrams 6-17Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.12 PCI
6-18 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.13 Operating Registers/SCRIPTS RAM Read, 32
PCI and External Memory Interface Timing Diagrams 6-19Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.14 Oper
6-20 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.15 Operating Register/SCRIPTS RAM Write, 32
PCI and External Memory Interface Timing Diagrams 6-21Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.16 Oper
LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller 2-1Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
6-22 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.6.4.2 Initiator TimingTables 6.23 through 6.30 and F
PCI and External Memory Interface Timing Diagrams 6-23Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.17 Nonb
6-24 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 6.24 Burst Opcode Fetch, 32-Bit Address and Da
PCI and External Memory Interface Timing Diagrams 6-25Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.18 Burs
6-26 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 6.25 Back to Back Read, 32-Bit Address and Dat
PCI and External Memory Interface Timing Diagrams 6-27Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.19 Back
6-28 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 6.26 Back to Back Write, 32-Bit Address and Da
PCI and External Memory Interface Timing Diagrams 6-29Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.20 Back
6-30 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 6.27 Burst Read, 32-Bit Address and DataSymbol
PCI and External Memory Interface Timing Diagrams 6-31Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.21 Burs
Preface iiiVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.PrefaceThis book is the primary reference and technical man
2-2 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 2.1 LSI53C896 Block Diagram8 KbyteSCR
6-32 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 6.28 Burst Read, 64-Bit Address and DataSymbol
PCI and External Memory Interface Timing Diagrams 6-33Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.22 Burs
6-34 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 6.29 Burst Write, 32-Bit Address and DataSymbo
PCI and External Memory Interface Timing Diagrams 6-35Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.23 Burs
6-36 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 6.30 Burst Write, 64-Bit Address and DataSymbo
PCI and External Memory Interface Timing Diagrams 6-37Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.24 Burs
6-38 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.6.4.3 External Memory TimingTables 6.31 through 6.38
PCI and External Memory Interface Timing Diagrams 6-39Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 6.31 Exter
6-40 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.25 External Memory ReadCLK(Driven by System
PCI and External Memory Interface Timing Diagrams 6-41Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.25 Exte
PCI Functional Description 2-3Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.2.1 PCI Functional DescriptionThe LSI53C
6-42 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
PCI and External Memory Interface Timing Diagrams 6-43Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 6.32 Exter
6-44 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.26 External Memory WriteCLK(Driven by Syste
PCI and External Memory Interface Timing Diagrams 6-45Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.26 Exte
6-46 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 6.33 Normal/Fast Memory (≥ 128 Kbytes) Single
PCI and External Memory Interface Timing Diagrams 6-47Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.27 Norm
6-48 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 6.34 Normal/Fast Memory (≥ 128 Kbytes) Single
PCI and External Memory Interface Timing Diagrams 6-49Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.28 Norm
6-50 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.29 Normal/Fast Memory (≥ 128 Kbytes) Multip
PCI and External Memory Interface Timing Diagrams 6-51Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.29 Norm
2-4 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.2.1.1.2 I/O SpaceThe PCI specification defines
6-52 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.30 Normal/Fast Memory (≥ 128 Kbytes) Multip
PCI and External Memory Interface Timing Diagrams 6-53Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.30 Norm
6-54 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 6.35 Slow Memory (≥ 128 Kbytes) Read CycleSymb
PCI and External Memory Interface Timing Diagrams 6-55Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.31 Slow
6-56 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 6.36 Slow Memory (≥ 128 Kbytes) Write CycleSym
PCI and External Memory Interface Timing Diagrams 6-57Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.32 Slow
6-58 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.33 ≤ 64 Kbytes ROM Read CycleTable 6.37 ≤ 6
PCI and External Memory Interface Timing Diagrams 6-59Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.34 ≤ 64
6-60 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.6.5 SCSI Timing DiagramsTables 6.39 through 6.49 and
SCSI Timing Diagrams 6-61Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.36 Initiator Asynchronous ReceiveFig
PCI Functional Description 2-5Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.2.1.2.1 Interrupt Acknowledge CommandThe
6-62 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.38 Target Asynchronous ReceiveTable 6.42 Ta
SCSI Timing Diagrams 6-63Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 6.43 SCSI-1 Transfers (SE 5.0 Mbytes)Sy
6-64 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 6.45 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit
SCSI Timing Diagrams 6-65Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 6.47 Ultra SCSI SE Transfers 20.0 Mbyte
6-66 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.39 Initiator and Target Synchronous Transfe
Package Drawings 6-67Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.6.6 Package DrawingsThe signal names are listed a
6-68 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 6.50 Alphanumeric List by Signal NameA_DIFFSEN
Package Drawings 6-69Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 6.51 Alphanumeric List by BGA PositionNC A1
6-70 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.40 LSI53C896 329 BGA (Bottom View)
Package Drawings 6-71Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.41 LSI53C896 329 BGA Mechanical Drawing
2-6 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.2.1.2.3 I/O Read CommandThe I/O Read command
6-72 SpecificationsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 6.41 LSI53C896 329 BGA Mechanical Drawing (Sh
LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller A-1Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
A-2 Register SummaryVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Max_Lat 0x3F Read Only 4-16Min_Gnt 0x3E Read Only
A-3Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Chip Type (CTYPE) 0x46 Read Only 4-85Cumulative SCSI Byte Count (CS
A-4 Register SummaryVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Memory Move Write Selector (MMWS) 0xA4–0xA7 Read/W
A-5Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.SCSI First Byte Received (SFBR) 0x08 Read/Write 4-38SCSI Input Data
A-6 Register SummaryVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller B-1Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
B-2 External Memory Interface Diagram ExamplesVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure B.2 64 Kbyte Inte
B-3Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure B.3 128, 256, 512 Kbyte or 1 Mbyte Interface with 150 ns Mem
PCI Functional Description 2-7Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.2.1.2.9 Configuration Write CommandThe Co
B-4 External Memory Interface Diagram ExamplesVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure B.4 512 Kbyte Int
LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller IX-1Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved
IX-2 IndexVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.(DREQ) 4-58(DRS) 4-109(DSA) 4-50(DSCL[1:0]) 4-18(DSI) 4-17,
Index IX-3Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.(PMJCTL) 4-102(PST) 4-18(PWS[1:0]) 4-18(QEN) 4-94(QSEL) 4-94
IX-4 IndexVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.(VER[2:0]) 4-17(VUE0) 4-28(VUE1) 4-29(WATN) 4-23(WIE) 4-4(WO
Index IX-5Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.B_SI_O+- 3-18B_SMSG+- 3-18B_SREQ+- 3-18B_SREQ2+- 3-18B_SRST+
IX-6 IndexVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.DD1_Support (D1S) 4-17D2_Support (D2S) 4-17data(DATA) 4-19ac
Index IX-7Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.even parity 2-27expansion ROM base address 2-56, 2-57, 4-13e
IX-8 IndexVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.memory move 5-35read/write instruction 5-23transfer control
Index IX-9Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.mailbox one (MBOX1) 2-43, 4-55mailbox zero (MBOX0) 2-43, 4-5
2-8 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Burst Size Selection – The Read Multiple com
IX-10 IndexVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.interface signals 3-5master transaction 2-12master transfer
Index IX-11Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.RAM 2-4, 2-21running (SRUN) 4-54SCSIATN condition - target
IX-12 IndexVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.20.0 Mbytes (16-bit transfers)40 MHz Clock 6-6450 MHz Clock
Index IX-13Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.test data in 3-20test data out 3-20test halt SCSI clock 3-2
IX-14 IndexVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction ControllerVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Cust
Customer FeedbackVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Reader’s CommentsFax your comments to: LSI Logic Corp
PCI Functional Description 2-9Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Read Multiple with Read Line Enabled – W
2-10 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.cache line size, but rather a multiple of t
PCI Functional Description 2-11Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.2.1.3 Internal ArbiterThe PCI to SCSI c
iv PrefaceVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.• Appendix B, External Memory Interface Diagram Examples,con
2-12 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.• The part must be doing a PCI Master trans
PCI Functional Description 2-13Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.smaller than the burst length, all byte
2-14 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 2.2 PCI Cache Mode AlignmentHost Memo
PCI Functional Description 2-15Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.2.1.4.5 ExamplesThe examples in this se
2-16 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Read Example 2 – Burst = 8 Dwords; Cache Li
PCI Functional Description 2-17Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Write Example 1 – Burst = 4 Dwords; Cac
2-18 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Write Example 2 – Burst = 8 Dwords; Cache L
SCSI Functional Description 2-19Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Write Example 3 – Burst = 16 Dwords; C
2-20 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.signal on the SCSI bus is used in error rec
SCSI Functional Description 2-21Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.The Phase Mismatch Jump logic powers u
Preface vVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Revision RecordRevision Date Remarks0.5 7/1997 Advanced Infor
2-22 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.2.2.3 64-Bit Addressing in SCRIPTSThe LSI53
SCSI Functional Description 2-23Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.2.2.5 Designing an Ultra2 SCSI SystemB
2-24 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.3. Halt the SCSI clock by setting the Halt
SCSI Functional Description 2-25Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.• On every Store instruction.The Store
2-26 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.occurring, any external PCI slave cycles th
SCSI Functional Description 2-27Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.2.2.11 Parity OptionsThe LSI53C896 imp
2-28 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 2.3 Bits Used for Parity Control and
SCSI Functional Description 2-29Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Table 2.4 SCSI Parity ControlEPC11. EP
2-30 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 2.2 Parity Checking/GenerationPCI In
SCSI Functional Description 2-31Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.2.2.12 DMA FIFOThe DMA FIFO is 8 bytes
vi PrefaceVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
2-32 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.2.2.13 Data PathsThe data path through the
SCSI Functional Description 2-33Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.significant bits of the DMA Byte Counte
2-34 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.register, then the least significant byte or
SCSI Functional Description 2-35Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.DMA FIFO (DFIFO) register. AND the res
2-36 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Bits 7 and 6 of the SCSI Test Four (STEST4)
SCSI Functional Description 2-37Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 2.5 8-Bit HVD Wiring Diagram fo
2-38 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.To interface the LSI53C896 to the SN75976A,
SCSI Functional Description 2-39Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.(or active) termination is recommended
2-40 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.2.2.15 Select/Reselect during Selection/Res
SCSI Functional Description 2-41Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 2.7 Determining the Synchronous
Contents viiVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.ContentsChapter 1 Introduction1.1 General Description 1-11
2-42 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.2.2.16.3 SCSI Control Three (SCNTL3) Regist
SCSI Functional Description 2-43Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.2.2.17 Interrupt HandlingThe SCRIPTS p
2-44 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Refer to Register 0x14, Interrupt Status Ze
SCSI Functional Description 2-45Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.interrupts flush neither the DMA nor SC
2-46 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.When operating in the Target mode, CMP, SEL
SCSI Functional Description 2-47Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.When the LSI53C896 is initialized, ena
2-48 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.A related situation to interrupt stacking i
SCSI Functional Description 2-49Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.2.2.17.7 Sample Interrupt Service Rout
2-50 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.2.2.18 Interrupt RoutingThis section docume
SCSI Functional Description 2-51Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 2.8 Interrupt Routing Hardware
viii ContentsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.2.2.9 JTAG Boundary Scan Testing 2-262.2.10 SCSI Loopback
2-52 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.2.2.19 Chained Block MovesBecause the LSI53
SCSI Functional Description 2-53Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.2.2.19.1 Wide SCSI Send BitThe WSS bit
2-54 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.2.2.19.3 SWIDE RegisterThis register stores
Parallel ROM Interface 2-55Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.and the transfer takes place normally. For
2-56 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.required, a 7406 (high voltage open collect
Serial EEPROM Interface 2-57Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.The LSI53C896 allows the system to determi
2-58 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.2.4.2 No Download ModeWhen MAD[7] is pulled
Power Management 2-59Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.LSI53C896 power states shown in Table 2.9 are ind
2-60 Functional DescriptionVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.2.5.3 Power State D2Power state D2 is a low
LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller 3-1Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Contents ixVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.3.6 Power and Ground Signals 3-213.7 MAD Bus Programming 3-
3-2 Signal DescriptionsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.Figure 3.1 LSI53C896 Functional Signal Grouping
3-3Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.There are five signal type definitions:I Input, a standard input-only
3-4 Signal DescriptionsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.3.1 Internal Pull-ups on LSI53C896 SignalsSever
PCI Bus Interface Signals 3-5Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.3.2 PCI Bus Interface SignalsThe PCI Bus
3-6 Signal DescriptionsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.3.2.2 Address and Data SignalsTable 3.3 describ
PCI Bus Interface Signals 3-7Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.3.2.3 Interface Control SignalsTable 3.4
3-8 Signal DescriptionsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.3.2.4 Arbitration SignalsTable 3.5 describes th
PCI Bus Interface Signals 3-9Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.3.2.5 Error Reporting SignalsTable 3.6 de
3-10 Signal DescriptionsVersion 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.3.2.6 Interrupt SignalsTable 3.7 describes the
PCI Bus Interface Signals 3-11Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.3.2.7 SCSI Function A GPIO SignalsTable
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